Exemplary embodiments of the present invention relate to a fractional digital phase locked loop (PLL) with an analog phase error compensator, and more particularly, to a fractional digital phase locked loop with an analog phase error compensator capable of reducing excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.
Recently, a charge pump or a phase locked loop (hereinafter, referred to as PLL) have been mainly used to implement an RF frequency synthesizer for multiband mobile communication. However, analog circuit design technologies are integrated in the charge pump PLL and therefore, a separately additional analog RF library is required in addition to a design library that is provided during a standard digital CMOS process due to analog circuits and analog signal characteristics, such that the charge pump PLL is hard to be integrated with a digital baseband signal processing block using a digital CMOS process.
In addition, a nano digital CMOS process has been developed with the recent development of a process technology. As a result, the digital baseband signal processing block has been quickly developed by the nano digital CMOS process.
Since a digital circuit needs not to be redesigned so as to keep pace with development trends of nano technologies, the digital circuit may be easily adapted to manufacturing process technologies. However, an analog RF circuit needs to be redesigned each time process technologies are changed and an operating voltage thereof may also be small since a CMOS process technology is developed to a nanoscale.
Thereby, much time and cost are consumed so as to improve several problems at the time of the analog RF circuit design during the nano digital CMOS process. Accordingly, research and development for digital RF that gradually converts the analog RF circuit block into a digital type is being actively conducted.
In particular, the frequency synthesizer in an RF transceiver is a part that may be formed into an all digital type. The digital PLL frequency synthesizer is a long-established technology but has poor phase noise and jitter characteristics and thus, is not almost used as a local oscillator of the RF transceiver for mobile communication requiring high-quality phase noise.
In recent, however, a new type of an all digital PLL (hereinafter, referred to as ADPLL) has been developed by applying the digital PLL technology to the frequency synthesizer for mobile communication. In the related art, only a difference between the digital PLL and the ADPLL is a digitally controlled oscillator (hereinafter, referred to as DCO). There is a difference in that the related DCO is implemented as a digital logic but the recent DCO is implemented as an LC resonator.
Therefore, the LC resonance DCO has more excellent characteristics in the phase noise or the jitter noise than the DCO using the digital logic of the related art.
The LC resonance DCO adjusts an oscillation frequency by controlling fractional variations of capacitance of the LC resonator. Therefore, a capacitor bank is divided into a coarse adjustment bank and a fine adjustment bank. Therefore, the coarse adjustment bank of the DCO is used at the time of fixing a PPL lock so as to approach the desired PLL frequency and is handed over to a fine adjustment bank by a mode conversion signal at the time of approaching the targeted PLL frequency by the coarse adjustment bank, wherein the fine adjustment bank applies a lock to the targeted PLL frequency through fractional tracking.
The fractional phase error (e) used for the fractional tracking is generated by a time-to-digital converter (hereinafter, referred to as TDC) and a fractional phase difference between a reference clock and a DCO clock that is an output value of a digital controlled oscillator is compensated in an arithmetic phase detector according to the fractional phase error (e).
The phase noise performance of the digital PLL according to the related art is determined by the resolution of the fractional phase error (e) that can be detected by the TDC. That is, the higher the fractional phase error detection resolution of the TDC, the better the phase noise becomes. The fractional phase error detection resolution is determined by minimum delay time of a delay device such as an inverter chain. Further, the inverter chain of the TDC is operated using the DCO clock having a high frequency, such that large power consumption and noise may occur.
Therefore, the digital TDC basically has a limitation in the tolerable phase error detection resolution due to the delay time of the delay device, which is a main factor determining the phase noise in a loop band of the PLL. In addition, quantization error, nonlinearity, meta-stability, or the like, of the TDC make the phase locked loop non-linear, thereby causing fractional spurs.
The fractional spurs may be removed by an analog filter by the charge pump PLL of the related art, but may not be completely filtered by a loop filter of the digital PLL due to a truncation error of the digital filter.
In addition, the TDC is basically configured of the inverter chain, such that the TDC may be easily affected by power noise and induces large transient current. Therefore, the TDC additionally requires a power pin to which a large capacitor is attached.
The above technology configuration is a background art for helping understanding of the present invention but does not mean the related art well-known in the art to which the present invention pertains.